Designing your virtualization host requires a lot of information; how many VM’s will it host, what are the requirements of each VM, what to reserve for the host, how much resources to include for future needs, etc. At least you need information on the VM requirements meaning you need details like memory and processor usage, network and disk I/O. Those can be obtained by using MAP and exported to Excel for detailed analysis.
Once that information is available, you can sort things out and design the host from the cumulative requirements (still incorporating necessary host reserves and future expansion).
Many developments in hardware assist in Server Virtualization; hardware assisted virtualization in the processor architecture (Intel-VT, AMD-V), Data Execution Prevention (actually a security measure) which are all requirements for running Hyper-V. But how about Second Level Address Translation (Intel: Extended Page Tables, AMD: Nested Page Tables)? Those address translation technologies may be very important when virtualizing memory intensive workloads. Maybe even more important, how about Virtual Machine Queues or Virtual Machine Direct Connect? The more general term is Intel-VT for Connectivity, Intel VT-c. You can read about Intel VT-c here.
All Virtual Machines require networking and often contain more than one network adapter. Network I/O is one of those things that may become a serious load on the virtualization host because it handles all network I/O in memory and taxes the processor.
When designing the host, there is much more to consider than memory and the number of sockets and cores and basic storage and network connectivity. IDC published a white paper called “Optimizing Hardware for x86 Server Virtualization” (sponsored by Intel). It gives a great overview of what comprises a server virtualization host. Very much worth reading for those who design server virtualization hosts. You will then conclude that a server virtualization host is not your ordinary file and print server with a lot of memory and processor cores.